Programmable logic devices exist as a well-known type of integrated circuit that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
A recent development in FPGA technology involves providing FPGAs comprising a plurality of what are known as “standard cells.” These “standard cells” are provided inside an FPGA as functional blocks and have a set height. Notably, the term “standard cell” is not to imply that any standard, de facto or otherwise, exists, as standard cell size may vary from company to company. So, for example, logic blocks, such as a flip-flop, a NAND gate, and an inverter, among other well-known logic circuits, each will lay out with a same height, but may have different lengths. This height is conventionally dependent on pitch of a company's integrated circuit process for one or more interconnect or metal layers. A standard cell may be made up of several logic blocks, each with a same height, but possibly with different lengths. Thus, each standard cell will have a same height but may have varying lengths. Standard cells may be assembled for providing interconnectivity logic or “glue logic.” Thus, an FPGA may be connected to an embedded device to carry out complex tasks.
For an embedded core in an integrated circuit, such as an FPGA with an embedded microprocessor core, a portion of the integrated circuit is reserved for the embedded core and glue logic. This reserved area for an FPGA may mean removal of one or more CLBs and block memories, among other pre-designed circuit elements. In other words, as an FPGA is designed in a modular manner, some modules may be removed for insertion of a block, such as an embedded device (embedded core and glue logic). However, an existing FPGA layout having an area blocked out for an embedded device causes termination of some signals, namely, those signals having terminated conductive or “metal” lines previously extending into the reserved area. In contrast, other metal lines are not terminated, and thus extend over the reserved area. So lower metal layers may be affected and higher metal layers may not be affected by embedding of a core with respect to interconnectivity between the integrated circuit and the embedded device.
This duality of affected and unaffected metal layers is most noticeable in power and ground interconnectivity. In order to reduce effects of electro-migration, multiple paths are provided to power and ground. Prior to the present invention, these power and ground interconnects were done manually after embedded device and FPGA databases had been merged or integrated. Manually laying out connections by searching for available tracks was time consuming. This involved examining a complete placement of blocks with all routing to such blocks, and placement of a conductor between metal lines and dropping vias at junction points of immediately spaced-apart upper and lower metal lines. However, without such additional distribution of power and ground interconnectivity, current-resistance (IR) losses would be too great, and electro-migration effects could, in some instances, create gradual degradation of interconnects causing long term reliability issues. Not only was this interconnection process time consuming, it was an iterative process conventionally requiring multiple iterations of layout-versus-schematic (LVS) and design-rule-check (DRC) steps. Additionally, conventionally placement of “jumpers” was done near an input/output ring already congested with metal lines.
Accordingly, it would be desirable and useful to provide means for placement and routing of power and ground interconnects with less, if any, manual processing as compared with prior placement and routing of power and ground interconnects.